Synopsys updates IC Compiler II 2019 to double throughput

New technologies have been incorporated in the IC Compiler II place and route system by Synopsys. The IC Compiler II 2019 release delivers up to two times faster throughput with next-generation distributed parallelisation, intelligent scenario management, efficient infrastructure scaling, and inherent core engine algorithm acceleration, explains the company.

It is designed for designs across a wide range of vertical markets, including automotive, cloud computing, artificial intelliffence (AI), networking and wireless applications. Advances in IC Compiler II technologies deliver  10 per cent total power reduction, five per cent smaller area, five per cent better timing, and two times faster runtime, confirms Synopsys. Realtek has deployed the latest IC Compiler II technologies on its next-generation communication network designs to meet stringent power, performance, and area (PPA) budgets while speeding up time to results (TTR) for designs.

Key new technologies in IC Compiler II for superior QoR include a common physical optimisation infrastructure, new arc-based unified concurrent clock-and-data (CCD) optimisation, physically-aware logic re-synthesis, and dynamic voltage drop-driven power shaping. RedHawk Analysis Fusion IR drop-driven optimisation, exhaustive path-based analysis (PBA), and sign off accuracy within IC Compiler II result in unmatched design convergence, claims Synopsys. Speed-up improvements, including inherent core engine algorithm speed-up, intelligent scenario management, efficient hardware scaling, and flow concurrency, double the design throughput, the company continues.

Synopsys is the Silicon to Software partner for innovative companies developing electronic products and software applications. It is the world’s 15th largest software company, with a long history in electronic design automation (EDA) and semiconductor IP. It also focuses on software security and quality solutions.

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