Tektronix adopts new approach to PCIe Gen 3 and Gen 4 testing
PCIe testing conventions have been reworked, said Tektronix, as it launched the TMT4 margin tester. It delivers fast test time and is easy to set up and use, said Tektronix for results in minutes rather than hours or even days of set up and testing, which can often stretch costs to seven figures, said Tektronix.
The TMT4 margin tester is a specialised testing tool for design and validation of PCIe Gen 3 and Gen 4 motherboards, add-in cards and system designs. While PCIe testing normally requires complex test systems and engineers with deep expertise and knowledge, the TMT4 margin tester enables engineers at all levels of experience to evaluate the health of transmitter (Tx) and receiver (Rx) links faster than ever, claimed Tektronix.
It supports the majority of common PCIe form factors, including CEM, M.2, U.2, and U.3, with testing capabilities of up to 16 lanes across PCIe presets 0 to nine, using a single standard connector.
The TMT4 margin tester is unrivalled in its speed and versatility for PCIe testing, enabling users to conduct earlier and more frequent evaluation of board- or system-level link health during design and validation. The TMT4 tester is intended to complement full validation and compliance testing systems consisting of oscilloscopes and BERTs (bit error rate testers), by making it possible to uncover issues earlier in the design process prior to an in-depth examination using traditional equipment.
The TMT4 margin tester enables engineers at all levels of expertise to test PCIe devices across up to 160 combinations of lanes and presets in as little as 20 minutes at Gen 4 speeds. Multi-lane testing capabilities enable users to improve overall testing times by reducing the number of connection changes needed to perform testing.
The TMT4 margin tester is built on the Intel Stratix 10 FPGA with PCIe. It has quick scan mode to evaluate the link health for Gen 3 or Gen 4 devices, up to 16 lanes, in minutes. The custom scan mode provides deeper insights by enabling users to scan Gen 3 or 4 devices, up to 16 lanes, across PCIe presets 0 to nine (up to 160 combinations) in as little as 20 minutes.
There is full Tx/Rx protocol capability that enables link health evaluation of PCIe Gen 3 and Gen 4 communication technologies on both sides of the link in a single box.
The tester also has multi-lane testing capabilities to enable users to significantly improve overall testing times by reducing the number of connection changes needed to perform testing.
There is visibility of link training parameters to provide additional insights into which equalisation was used to form the link.
There is a choice of adapters supporting the most common PCIe form factors for easy connection to motherboard and add-in card DUTs including CEM, M.2, U.2 and U.3.
