Telexsus helps engineers assess PCI Express implementation
Teledyne LeCroy has spent years helping engineers design with PCIe. Its partner, Telexsus, offers solutions to address some of PCIe testing’s main challenges.
It looks at the latest updates to PCIe 4.0, PCIe 5.0 and beyond with PCIe 6.0, as well as useful debugging techniques for all generations of PCIe and how to validate designs using real-time error injection.
The free workshops give attendees the opportunity to run their add-in cards against the Teledyne LeCroy link and transaction layer compliance platform as used at PCI-SIG compliance workshops.
The PCI Express (PCIe) protocol can be found in desktop PCs, servers and their associated device cards, and also in medical, data storage, AI, aerospace and industrial control devices and systems.
For most engineers, their designs incorporate PCIe through use of CPUs and FPGAs, but there are also SoCs, ASICs, bridges, switches and other application-specific devices which use PCIe. This means that there are many devices to choose from and these may also support PCIe speeds of 2.5, five, eight, 16 and now 32Gtransfers per second, delivering many combinations. Developers also have to bear in mind that each generation of PCIe is designed to be backwards-compatible and, with all the potential combinations of host-device implementations, it is a real challenge to ensure every PCIe host and device communicates with each other. A PCIe switch or bridge device adds another level of complexity.
The PCI-SIG (Special Interest Group) provides a program for checking that PCIe designs meet the specifications through compliance workshops, although this is not a replacement for exhaustive validation. For example, PCIe link and transaction layer compliance testing is only performed at a one-link width, and no matter how many compliance workshops a product undergoes, it is impossible to have every PCIe host tested with every PCIe device.
The advent of devices such as Non Volatile Memory Express (NVMe) solid state devices (SSDs) means that there are complex, higher level protocols running over the PCIe link adding to the challenge of interoperability.
The Telexsus workshops address the challenges of establishing a PCIe link through the process of link training. This is the method by which the two devices on the link determine each other’s physical capabilities, such as link width and data rates supported. It is possible that during this process, the link does not establish with the expected width or data rate, resulting in a marked decrease in the throughput available on the link. For example, it can happen that two devices that support 8Gtransfers per second data rate yet only link at 2.5Gtransfers per second. The link may appear to function and be able to transfer data but the performance could be much below than expected.
Workshops also examine if the link is operating at the expected width and data rate but suffering from flow control starvation at the data link layer, resulting in intermittent performance and unexpected behaviour in the software applications utilising the PCIe link. Power management transitions such as those used by Active State Power Management (ASPM) can also impact performance and are often challenging to optimise and debug.
Finally, the application software running over the PCIe link directly impacts the behaviour of the system. Many issues are difficult to identify from just software tools running on the host system. Tapping in to observe the traffic on the link between the host and device is often a far more efficient way to identify the cause of the problem, observe and resolve issues, and in some cases, it is the only way to understand a failure and decide what needs to be done to correct it. Determining that a performance issue is related to flow control or link training issues is something that can only be observed using a protocol analyser.
Protocol analysers have provided this observability of the link for many years through all the generations of PCIe. The relaxation of the replay timer requirements in the PCIe 4.0 specification has also made it possible to introduce protocol jamming techniques into PCIe test tools. Modifying the traffic in an active PCIe link at all layers is now possible, providing engineers with the ability to create on-demand scenarios which show how a host or device handles specific errors or bus conditions.