Tessent RTL Pro streamlines IC design and DFT tasks, says Siemens

Software to help IC design teams streamline and accelerate a critical design-for-test (DFT) tasks has been announced by Siemens Digital Industries Software. The Tessent RTL Pro is the latest in the Tessent portfolio of design editing software.

As IC designs grow in both size and complexity, engineers must identify and address testability issues at the earliest possible stages of design, explained Siements. Tessent software helps customers meet this need by enabling the analysis and insertion of a large majority of DFT logic early in the design flow, performing quick synthesis and then running automatic test pattern generation (ATPG) to identify and address outlier blocks and take appropriate measures.

Tessent RTL Pro automates the analysis and insertion of test points, wrapper cells, and x-bounding logic early in the design flow, which can help customers shorten design cycles and improve testability of the designs. The software is distinctive in that it handles complex Verilog and SystemVerilog constructs while maintaining the look and feel of the original RTL design, said Siemens.

Tessent RTL Pro enables analysis of RTL complexity and its adaptability for test point insertion, evaluating whether the customer’s RTL structure can be edited efficiently, which is a critical factor when adding test points throughout the design and to reduce time-to-market.

A “shift-left” functionality also helps enhance the ability of third-party tools to optimise area and timing when adding DFT logic prior to synthesis, leaving only scan insertion for the gate level. Design insertion happens at the RTL development stage, with RTL output, allowing seamless integration with third party synthesis and verification software. The software also generates design files that work with any downstream synthesis or verification flows, without requiring a closed-flow process.

Ankur Gupta, vice president and general manager, Tessent division, Siemens Digital Industries Software, commented: “With the ability to analyse and insert wrapper cells, x-bounding logic, and VersaPoint test points at the RTL stage of design, customers can now extend their shift-left initiatives by substantially enhancing the testability of their designs”.

Renesas has adopted Tessent RTL Pro for its automotive semiconductor design. It allows the company to reduce the iterations of the conventional design flow while maintaining coverage and pattern count, said Tatsuya Saito, senior principal EDA engineer, Digital Design Technology Department, Shared R&D EDA Division Renesas Electronics. “The ability to provide our back end and verification teams with the same, complete design view containing all Tessent IP, including VersaPoint test points in RTL, is paramount for our competitiveness,” he added.


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