Verification IP from SmartDV supports Ethernet TSN

At DAC 2019, SmartDV Technologies unveiled verification IP to support Ethernet time-sensitive networking (TSN).

The IP complies with the updated IEEE standard for time-sensitive transmission of data over Ethernet networks, the IEEE 802.1, which defines components of time-sensitive networking.

SmartDV’s Ethernet TSN verification IP features a complete set of protocols, and verification and productivity tools to achieve accelerated verification closure of Ethernet-based designs used in real-time communications where timing and latency must meet critical time boundaries. It verifies a design’s MAC-to-PHY and PHY-to-MAC layer interfaces and works within a SystemVerilog, Verilog hardware description language (HDL), Vera or SystemC environment.

In addition to Ethernet TSN, SmartDV offers a range of Ethernet verification IP to support 10, 100, 1G, 10G, 40G, 100G, 200G and 400G Ethernet. All are IEEE 802.3 compliant.

The SmartDV Ethernet TSN verification IP is fully functional and shipping now.

SmartDV Technologies employs over 250 experienced ASIC and SoC design and verification engineers to provide verification and design IP. SmartDV’s standard or custom protocol verification and design IP is compatible with all verification languages, platforms and methodologies supporting all simulation, emulation and formal verification tools used in a coverage-driven chip design verification flow.

Its verification and design IP is used in networking, storage, automotive, bus, MIPI and display chip projects.

SmartDV is headquartered in Bangalore, India, with US headquarters in San Jose, California, USA.

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