Xilinx Zynq UltraScale+ FPGA board addresses wireless infrastructure
Integrated systems, embedded boards, software and application-ready platform manufacturer, VadaTach, announces the AMC541 board. It couples a Xilinx Zynq Ultrascale+ XCZU19EG MPSoC FPGA with the TCI6638K2K communications KeyStone SoC in the high performance wireless infrastructure module.
Xilinx’s Zynq Ultrascale+ XCZU19EG MPSoC FPGA includes an embedded quad-core Arm Cortex-A53 application processing unit, a Dualcore Arm Cortex-R5 real-time processing unit and an Arm Mali – MP2 graphics processing unit (GPU). The FPGA has dual banks of 64-bit DDR4 memory (one bank to the Arm core and one bank to the FPGA) and includes an SD card.
The TCI6638K2K communications infrastructure KeyStone SoC is a member of the C66x family based on TI’s new KeyStone II multicore SoC architecture designed specifically for high-performance telecommunications, internet of things (IoT) and networking applications. It features eight TMS320C66x DSP core subsystems (C66x CorePacs). The TMS320C66x interfaces to dual 64-bit wide DRAM DDR-3.
The flexible AMC541 architecture allows the FPGA and DSP to interface to the AMC connector in different configurations. The AMC connector ports two to three and eight to 11 are linked directly to the FPGA for the core to interface with the host through protocols such as SRIO, PCIe or 10/40GbE. Ports four to seven can connect directly to the FPGA in addition to ports eight to 11, or connect directly to the DSP with SRIO protocol via MUX (DIP-switch selection). The module also routes GbE on ports 0 and 1 per AMC.2 while the DSP and FPGA are linked via PCIe x2 and GbE. The on-board, re-configurable FPGA interfaces to the AMC FCLKA (fabric clock) and TCLKA-D (user clocks and triggers) via a clock and jitter cleaner. There is also a front panel TRIG IN and CLK IN to the clock and jitter cleaner – the three front panel SFP+ cages allow expansion via fibre or copper interface.
