Xtensa processors meet ISO 26262 compliance to ASIL-D
Cadence Tensilica Xtensa processors with FlexLock capability meet the ISO 26262:2018 standard to ASIL-D, the highest level possible under the Automotive Safety Integrity Level rating. The functional safety certification spans from base microcontroller to high-performance DSP, each with a configuration option for FlexLock to provide increased random fault protection. The processor have been developed following a robust safety process to protect against systematic faults. Tensilica Xtensa processors with FlexLock are suitable for the automotive market and tailored for AI, vision, radar, lidar, audio, vehicle-to-everything (V2X), and control applications.
The Cadence Tensilica FlexLock processors optimised for automotive applications are among the first in the industry to achieve full compliance with ASIL-D functional safety standards, said Wolfgang Ruf, head of functional safety for semiconductors at SGS-TÜV Saar. “Certification to . . . . the ISO 26262:2018 standard for ASIL-D systematic and random fault avoidance is a testament to the high functional safety quality of Cadence’s IP. SoC designers are assured that their designs using functional safety-certified Tensilica processor IP can achieve compliance with the automotive industry’s stringent safety-critical requirements,” he added.
Key to ASIL-D compliance is the new FlexLock capability, which adds lockstep support to the flexible and extensible Xtensa processor architecture. Lockstep is a proven method for increasing safety in software execution by providing redundancy of the core logic at the hardware level. In addition to ASIL-D certification, FlexLock also gives design teams the ability to accommodate two cores running independently in ASIL-B solutions and the option of running local memories and caches of two cores in lockstep, achieving even greater levels of protection against memory faults.
“Higher levels of autonomy require more intelligent computing at the edge in automotive applications, which is driving the need for higher levels of functional safety,” said Larry Przywara, senior group director, Tensilica marketing at Cadence. “With the introduction of FlexLock capability, users of Tensilica controllers and DSPs can achieve the highest level of certification, ASIL-D, and the protection it brings against random hardware faults. Designers choosing Tensilica IP to accelerate their ADAS [advanced driver assistance systems], radar, lidar, V2X and vision processing can do so with the confidence that they can meet their customers’ functional safety requirements.”
As with other Xtensa processors, the ASIL-D certified cores can be customised using the Tensilica Instruction Extension (TIE) language. This allows the IP to be optimised for the specific application, combining the right level of performance with the highest levels of safety.
The Tensilica Xtensa processors with FlexLock capability are available now.
