Xylon releases multi-channel HDR ISP IP suite for multiple video processing

For use with Xilinx programmable devices, ranging from the Artix-7 FPGAs to the latest Versal ACAP devices, the logicBricks high dynamic range (HDR) image signal processing (ISP) IP Suite enables parallel processing of multiple Ultra-HD video inputs. At the same time, it allows savings of up to 50 per cent of programmable logic in comparison to simple instantiation of multiple ISP pipelines, says Xylon.

The latest version of Xylon’s logicBricks IP suite enables crisp camera video under altering and rough lighting conditions in next-generation, multi-channel embedded systems for use in automotive, surveillance, medical and similar video and vision artificial intelligence (AI) applications.

The logicBricks HDR ISP IP suite is designed and optimised for Xilinx programmable devices.

“As the automotive industry progressively moves towards more automated driving implementations, the trend towards high resolution cameras and higher frame rates continues,” said Paul Zoratti, director of automotive solutions and system architect at Xilinx. The multi-camera ISP functionality will help automotive developers optimise cost, power, and performance in future advanced driver assistance systems (ADAS) and automated driving products, he added.

The suite’s key IP cores, the logiISP-UHD ISP pipeline and the logiHDR HDR pipeline, support parallel processing of multiple video inputs, resolutions up to 7680 x 7680 (including the popular 4K2Kp60 video resolution). It also supports the ability to merge two or three exposures, parallel pixel processing and different pixel formats. These IP cores are supplemented with automatic white balance (AWB) and automatic exposure (AE) software libraries that use video statistics data collected at the video inputs, software drivers, demo applications, reference SoC designs, and bit-accurate C models.

The HDR ISP IP suite enables application-specific tuning through modifications at different implementation stages, explained Roko Koncurat, Xylon’s ISP team lead. “The provided IP blocks can be arranged in many different ways to fully tune up the system for a specific application. While hardware engineers may configure and arrange IP blocks implemented in programmable logic in various ways, software engineers can further control the implemented ISP pipeline to adapt to changing use conditions,” he said.

The logicBricks HDR ISP IP suite can be demonstrated on different computer vision development platforms designed by Xylon. The  logiREF-MULTICAM-ISP reference design is immediately available. It demonstrates parallel processing of four video camera inputs and works on the logiISP-ZU-GMSL2 evaluation kit. This kit is based on the Xilinx Zynq UltraScale+ MPSoC and includes four of Xylon’s 2.3 MP HDR logiCAM-GMSL2 automotive cameras configured to output raw Bayer video image. Xylon’s automotive cameras are Xilinx Artix-7 FPGA-based and users can re-install the HDR ISP functionality with the provided firmware and initialisation scripts.   

In addition to the MPSoC-based demo kit, Xylon offers an Ultra HD reference design prepared for the logiVID-ACAP vision development kit based on the Xilinx Versal AI VCK190 evaluation kit. The reference design is developed with the Xilinx Vitis unified software platform and demonstrates parallel HDR ISP processing of three 7.4Mpixel automotive video cameras connected to the Xilinx Versal (ACAP) device.


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