IP core interfaces with Xilinx FPGAs

Framos has launched the SLVS-EC RX IP core for sensor interfacing with FPGAs from Xilinx. The proprietary FRAMOS FPGA module is available with an evaluation kit and connects Sony’s high-speed SLVS-EC interface with Xilinx FPGAs allowing vision engineers to seamlessly upgrade to Sony’s interface technology.

The IP provides the technological basis for future camera developments and embedded vision devices.

Framos developed the RX IP core to reduce overhead and complexity implementing a Sony imager with SLVS-EC. As an on-chip function block connecting the customer’s FPGA logic with the image sensor’s data stream, the IP core receives the interface data, manages the byte-to-pixel conversion for various lane configurations and prepares a highly-efficient processing workflow run on the FPGA. The Framos software supports SLVS-EC v1.2 with one, two, four or eight lanes configurable by the user and delivers pixels formats from eight to 14-bit of raw data. By de-risking the sensor implementation it significantly reduces the development efforts and accelerates the time to market, claims the company.

“SLVS-EC is the benchmark interface standard of the future for high-speed data transfer from Sony imagers,” explained Simon Che’Rose, head of development at Framos. “It uplifts existing and upcoming CMOS designs to the next speed and performance level and supports miniaturisation,” he added. “Our RX IP core block for Xilinx FPGAs, in combination with the full documented evaluation kit, makes integration and system development easy, resulting in a faster time to market for customer applications working with SLVS-EC.”

As an official Xilinx partner, Framos works in close cooperation with Xilinx. The SLVS-EC RX IP core works with the main existing and upcoming FPGA families. The package includes the encrypted RTL IP Core with a simulation environment (ModelSim) and dedicated reference design examples. The kit provides designs to guide and test the implementation of a SLVS-EC based sensor, including the hardware and software environment and documented implementation examples with source codes.


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