Software accelerates artificial intelligence workloads
Artificial intelligence (AI) –specific tiles make up a library used by eSilicon in its 7nm FinFET newASIC AI IP platform. The AI Accelerator tiles can be configured to support an AI algorithm and map high-level AI workloads to the neuASIC platform and estimate power, performance, area (PPA) for the algorithm in the silicon implementation.
The combination of neuASIC IP and the AI Accelerator software allows designers to explore architectures to ensure the design will be within the target specifications. eSilicon explains that this approach supports changes to the algorithm or the package.
AI Accelerator is available in IP Navigator, eSilicon’s IP exploration and evaluation tool, at no charge.
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging. The ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimised 16/14/7nm FinFET IP platforms featuring HBM2 (high bandwidth memory) PHY (physical layer), ternary content-addressable memory (TCAM), specialised memory compilers and I/O libraries.
The neuASIC platform provides AI-specific IP and a modular design methodology to create adaptable, efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets.