MIPS previews its first RISC-V IP

Two multiprocessors IP cores, the eVocore P8700 and I8500 mark MIPS entry to the RISC-V market. The multiprocessor IP cores are based on the RISC-V open instruction set architecture (ISA) standard.  

CEO Desi Banatao commented on the IP introduction: “By leveraging our differentiation in real-time features, hardware virtualisation, functional safety and security technologies, we can offer compelling products for automotive, edge compute, networking and switching, and large-scale computing systems”.

The scalable and configurable RISC-V-compatible eVocore IP cores are designed to enable customers to blend coherent clusters of multi-threaded, multi-core CPUs in combinations which meet exact power and performance requirements. The cores are designed to provide a flexible foundation for heterogeneous compute, supporting combinations of eVocore processors as well as other accelerators, with a Coherence Manager that maintains L2 cache and system-level coherency between all cores, main memory and I/O devices. 

The RISC-V ISA enables custom features to be added in the form of user defined instructions (UDIs). MIPS explained that it can therefore deliver proven features while also being compatible with off the shelf RISC-V development tools and software libraries. 

Both eVocore IP cores provide support for privileged hardware virtualisation, user defined custom extensions, multi-threading, hybrid debug and functional safety. They are therefore suitable for compute-intensive tasks across a range of markets and applications, including automotive (in ADAS, autonomous vehicles and IVI or in-vehicle infotainment), 5G and wireless networking, data centre and storage and high-performance embedded applications.

The eVocore P8700 multiprocessing system combines a deep pipeline with multi-issue out-of-rrder (OOO) execution and multi-threading for computational throughput. It can scale up to 64 clusters, 512 cores and 1,024 harts/threads. It will be available in Q4 2022.

eVocore I8500 is the second IP core. This in-order multiprocessing system has power efficiency performance suitable for SoC applications. Each I8500 core combines multi-threading and an efficient triple-issue pipeline to deliver computational throughput. 

According to Semico Research, the CAGR for SoCs shipping with RISC-V CPU cores between 2020 and 2027 is 73.6 per cent and the automotive segment is projected to achieve a 69.9 per cent CAGR in that period.

MIPS develops scalable RISC processor IP for automotive, computing and communications applications. Its engineering expertise has been built over 35 years and the company has shipped billions of MIPS-based chips to date. 


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